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authorEugen Wissner <belka@caraus.de>2024-10-04 18:26:10 +0200
committerEugen Wissner <belka@caraus.de>2024-10-04 18:26:10 +0200
commit35742aa52587400950cf25170c2247f98f498d4d (patch)
tree78d0fd208e2e08d30c18ada33c52bc76a91267d6 /lib/Language/Elna/RiscV/CodeGenerator.hs
parentfdf56ce9d0de459dc5bd65537847ded7b02ad5c2 (diff)
downloadelna-35742aa52587400950cf25170c2247f98f498d4d.tar.gz
Add printc and exit builtin functions
Diffstat (limited to 'lib/Language/Elna/RiscV/CodeGenerator.hs')
-rw-r--r--lib/Language/Elna/RiscV/CodeGenerator.hs26
1 files changed, 26 insertions, 0 deletions
diff --git a/lib/Language/Elna/RiscV/CodeGenerator.hs b/lib/Language/Elna/RiscV/CodeGenerator.hs
index d20488c..439f99c 100644
--- a/lib/Language/Elna/RiscV/CodeGenerator.hs
+++ b/lib/Language/Elna/RiscV/CodeGenerator.hs
@@ -132,6 +132,32 @@ quadruple (NegationQuadruple operand1 (Store register))
$ RiscV.BaseInstruction RiscV.Op
$ RiscV.R register RiscV.SUB RiscV.Zero operandRegister1
$ RiscV.Funct7 0b0100000
+quadruple (ProductQuadruple operand1 operand2 (Store register))
+ | IntOperand immediateOperand1 <- operand1
+ , IntOperand immediateOperand2 <- operand2 =
+ lui (immediateOperand1 * immediateOperand2) register
+ | VariableOperand variableOperand1 <- operand1
+ , VariableOperand variableOperand2 <- operand2 =
+ let Store operandRegister1 = variableOperand1
+ Store operandRegister2 = variableOperand2
+ in pure $ Instruction
+ $ RiscV.BaseInstruction RiscV.Op
+ $ RiscV.R register RiscV.MUL operandRegister1 operandRegister2 (RiscV.Funct7 0b0000001)
+ | VariableOperand variableOperand1 <- operand1
+ , IntOperand immediateOperand2 <- operand2 =
+ multiplyImmediateRegister variableOperand1 immediateOperand2
+ | IntOperand immediateOperand1 <- operand1
+ , VariableOperand variableOperand2 <- operand2 =
+ multiplyImmediateRegister variableOperand2 immediateOperand1
+ where
+ multiplyImmediateRegister variableOperand immediateOperand =
+ let statements = lui immediateOperand register
+ Store operandRegister = variableOperand
+ in Vector.snoc statements
+ $ Instruction
+ $ RiscV.BaseInstruction RiscV.Op
+ $ RiscV.R register RiscV.MUL register operandRegister
+ $ RiscV.Funct7 0b0000001
loadImmediateOrRegister :: RiscVOperand -> RiscV.XRegister -> (RiscV.XRegister, Vector Statement)
loadImmediateOrRegister (IntOperand intValue) targetRegister =