From 35742aa52587400950cf25170c2247f98f498d4d Mon Sep 17 00:00:00 2001
From: Eugen Wissner <belka@caraus.de>
Date: Fri, 4 Oct 2024 18:26:10 +0200
Subject: Add printc and exit builtin functions

---
 lib/Language/Elna/RiscV/CodeGenerator.hs | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'lib/Language/Elna/RiscV/CodeGenerator.hs')

diff --git a/lib/Language/Elna/RiscV/CodeGenerator.hs b/lib/Language/Elna/RiscV/CodeGenerator.hs
index d20488c..439f99c 100644
--- a/lib/Language/Elna/RiscV/CodeGenerator.hs
+++ b/lib/Language/Elna/RiscV/CodeGenerator.hs
@@ -132,6 +132,32 @@ quadruple (NegationQuadruple operand1 (Store register))
             $ RiscV.BaseInstruction RiscV.Op
             $ RiscV.R register RiscV.SUB RiscV.Zero operandRegister1
             $ RiscV.Funct7 0b0100000
+quadruple (ProductQuadruple operand1 operand2 (Store register))
+    | IntOperand immediateOperand1 <- operand1
+    , IntOperand immediateOperand2 <- operand2 =
+        lui (immediateOperand1 * immediateOperand2) register
+    | VariableOperand variableOperand1 <- operand1
+    , VariableOperand variableOperand2 <- operand2 =
+        let Store operandRegister1 = variableOperand1
+            Store operandRegister2 = variableOperand2
+        in pure $ Instruction
+            $ RiscV.BaseInstruction RiscV.Op
+            $ RiscV.R register RiscV.MUL operandRegister1 operandRegister2 (RiscV.Funct7 0b0000001)
+    | VariableOperand variableOperand1 <- operand1
+    , IntOperand immediateOperand2 <- operand2 =
+        multiplyImmediateRegister variableOperand1 immediateOperand2
+    | IntOperand immediateOperand1 <- operand1
+    , VariableOperand variableOperand2 <- operand2 =
+        multiplyImmediateRegister variableOperand2 immediateOperand1
+  where
+    multiplyImmediateRegister variableOperand immediateOperand = 
+        let statements = lui immediateOperand register
+            Store operandRegister = variableOperand
+        in Vector.snoc statements
+            $ Instruction
+            $ RiscV.BaseInstruction RiscV.Op
+            $ RiscV.R register RiscV.MUL register operandRegister
+            $ RiscV.Funct7 0b0000001
 
 loadImmediateOrRegister :: RiscVOperand -> RiscV.XRegister -> (RiscV.XRegister, Vector Statement)
 loadImmediateOrRegister (IntOperand intValue) targetRegister =
-- 
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