From 0c40bca60b343bb289f0a567ec9ec9e9382bad2a Mon Sep 17 00:00:00 2001
From: Eugen Wissner <belka@caraus.de>
Date: Mon, 2 Dec 2024 13:57:03 +0100
Subject: Add array assignment to the IR

---
 lib/Language/Elna/RiscV/CodeGenerator.hs | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

(limited to 'lib/Language/Elna/RiscV/CodeGenerator.hs')

diff --git a/lib/Language/Elna/RiscV/CodeGenerator.hs b/lib/Language/Elna/RiscV/CodeGenerator.hs
index a0ad5f9..6e7a8cd 100644
--- a/lib/Language/Elna/RiscV/CodeGenerator.hs
+++ b/lib/Language/Elna/RiscV/CodeGenerator.hs
@@ -259,6 +259,42 @@ quadruple _ (AssignQuadruple operand1 store)
                 $ RiscV.BaseInstruction RiscV.OpImm
                 $ RiscV.I storeRegister RiscV.ADDI operandRegister1 0
          in pure $ statements1 <> Vector.cons instruction storeStatements 
+quadruple _ (ArrayAssignQuadruple assigneeOperand indexOperand store)
+    | IntOperand immediateAssigneeOperand <- assigneeOperand =
+        let (storeRegister, storeStatements) = storeWithOffset store indexOperand
+         in pure $ lui immediateAssigneeOperand storeRegister <> storeStatements
+    | VariableOperand variableAssigneeOperand <- assigneeOperand =
+        let (assigneeOperandRegister, assigneeStatements) = loadFromStore variableAssigneeOperand
+            (storeRegister, storeStatements) = storeWithOffset store indexOperand
+            instruction = Instruction
+                $ RiscV.BaseInstruction RiscV.OpImm
+                $ RiscV.I storeRegister RiscV.ADDI assigneeOperandRegister 0
+         in pure $ assigneeStatements <> Vector.cons instruction storeStatements 
+  where
+    storeWithOffset :: RiscVStore -> Operand RiscVStore -> (RiscV.XRegister, Vector Statement)
+    storeWithOffset (RegisterStore register) _ = (register, mempty)
+    storeWithOffset (StackStore offset register) (IntOperand indexOffset) =
+        let storeInstruction = Instruction
+                $ RiscV.BaseInstruction RiscV.Store
+                $ RiscV.S (fromIntegral $ offset + indexOffset) RiscV.SW RiscV.S0 register
+        in (register, Vector.singleton storeInstruction)
+    storeWithOffset (StackStore offset register) (VariableOperand indexOffset) =
+        let baseRegisterInstruction = Instruction
+                $ RiscV.BaseInstruction RiscV.OpImm
+                $ RiscV.I immediateRegister RiscV.ADDI RiscV.S0 0
+            (indexRegister, indexStatements) = loadFromStore indexOffset
+            registerWithOffset = Instruction
+                $ RiscV.BaseInstruction RiscV.OpImm
+                $ RiscV.I immediateRegister RiscV.ADDI indexRegister 0
+            storeInstruction = Instruction
+                $ RiscV.BaseInstruction RiscV.Store
+                $ RiscV.S (fromIntegral offset) RiscV.SW immediateRegister register
+            statements = Vector.fromList
+                [ baseRegisterInstruction
+                , registerWithOffset
+                , storeInstruction
+                ]
+        in (register, indexStatements <> statements)
 
 unconditionalJal :: Label -> Statement
 unconditionalJal (Label goToLabel) = Instruction
-- 
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