Implement the while loop

1 files changed, 4 insertions, 4 deletions

diff --git a/lib/Language/Elna/RiscV/CodeGenerator.hs b/lib/Language/Elna/RiscV/CodeGenerator.hs
index 15e8723..a0ad5f9 100644
--- a/lib/Language/Elna/RiscV/CodeGenerator.hs
+++ b/lib/Language/Elna/RiscV/CodeGenerator.hs
@@ -98,7 +98,7 @@ generateRiscV = flip evalState 0
 
 quadruple :: Word32 -> RiscVQuadruple -> RiscVGenerator (Vector Statement)
 quadruple stackSize StartQuadruple =
-    let totalStackSize = stackSize + 4
+    let totalStackSize = stackSize + 8
      in pure $ Vector.fromList
         [ Instruction (RiscV.BaseInstruction RiscV.OpImm $ RiscV.I RiscV.SP RiscV.ADDI RiscV.SP (negate totalStackSize))
         , Instruction (RiscV.BaseInstruction RiscV.Store $ RiscV.S 0 RiscV.SW RiscV.SP RiscV.S0)
@@ -106,7 +106,7 @@ quadruple stackSize StartQuadruple =
         , Instruction (RiscV.BaseInstruction RiscV.OpImm $ RiscV.I RiscV.S0 RiscV.ADDI RiscV.SP totalStackSize)
         ]
 quadruple stackSize StopQuadruple =
-    let totalStackSize = stackSize + 4
+    let totalStackSize = stackSize + 8
      in pure $ Vector.fromList
         [ Instruction (RiscV.BaseInstruction RiscV.Load $ RiscV.I RiscV.S0 RiscV.LW RiscV.SP 0)
         , Instruction (RiscV.BaseInstruction RiscV.Load $ RiscV.I RiscV.RA RiscV.LW RiscV.SP 4)
@@ -438,7 +438,7 @@ loadFromStore (RegisterStore register) = (register, mempty)
 loadFromStore (StackStore offset register) =
     let loadInstruction = Instruction
             $ RiscV.BaseInstruction RiscV.Load
-            $ RiscV.I register RiscV.LW RiscV.S0 offset
+            $ RiscV.I register RiscV.LW RiscV.S0 (fromIntegral offset)
      in (register, Vector.singleton loadInstruction)
 
 storeToStore :: RiscVStore -> (RiscV.XRegister, Vector Statement)
@@ -446,5 +446,5 @@ storeToStore (RegisterStore register) = (register, mempty)
 storeToStore (StackStore offset register) =
     let storeInstruction = Instruction
             $ RiscV.BaseInstruction RiscV.Store
-            $ RiscV.S offset RiscV.SW RiscV.S0 register
+            $ RiscV.S (fromIntegral offset) RiscV.SW RiscV.S0 register
      in (register, Vector.singleton storeInstruction)