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| author | Eugen Wissner <belka@caraus.de> | 2024-10-30 14:12:51 +0100 |
|---|---|---|
| committer | Eugen Wissner <belka@caraus.de> | 2024-10-30 14:12:51 +0100 |
| commit | 43882a3a0697945b35194c2b5940605e9f4dd846 (patch) | |
| tree | 494bde0fec422937f26b7b1a954adbcd477f7a9b /lib/Language/Elna/RiscV/CodeGenerator.hs | |
| parent | 6b92e5059c04709b3506bb4e7bef29872b16811f (diff) | |
| download | elna-43882a3a0697945b35194c2b5940605e9f4dd846.tar.gz | |
Generate a call to _divide_by_zero_error on RiscV
Diffstat (limited to 'lib/Language/Elna/RiscV/CodeGenerator.hs')
| -rw-r--r-- | lib/Language/Elna/RiscV/CodeGenerator.hs | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/lib/Language/Elna/RiscV/CodeGenerator.hs b/lib/Language/Elna/RiscV/CodeGenerator.hs index 6e5a92f..4be7dfd 100644 --- a/lib/Language/Elna/RiscV/CodeGenerator.hs +++ b/lib/Language/Elna/RiscV/CodeGenerator.hs @@ -234,20 +234,31 @@ quadruple (DivisionQuadruple operand1 operand2 (Store register)) , IntOperand immediateOperand2 <- operand2 = let statements2 = lui immediateOperand2 register Store operandRegister1 = variableOperand1 - in pure $ Vector.snoc statements2 - $ Instruction - $ RiscV.BaseInstruction RiscV.Op - $ RiscV.R register RiscV.DIV operandRegister1 register - $ RiscV.Funct7 0b0000001 + operationInstruction + | immediateOperand2 == 0 = + RiscV.CallInstruction "_divide_by_zero_error" + | otherwise = RiscV.BaseInstruction RiscV.Op + $ RiscV.R register RiscV.DIV operandRegister1 register + $ RiscV.Funct7 0b0000001 + in pure $ Vector.snoc statements2 + $ Instruction operationInstruction | IntOperand immediateOperand1 <- operand1 - , VariableOperand variableOperand2 <- operand2 = + , VariableOperand variableOperand2 <- operand2 = do let statements1 = lui immediateOperand1 register Store operandRegister2 = variableOperand2 - in pure $ Vector.snoc statements1 - $ Instruction - $ RiscV.BaseInstruction RiscV.Op - $ RiscV.R register RiscV.DIV register operandRegister2 - $ RiscV.Funct7 0b0000001 + divisionInstruction = Instruction + $ RiscV.BaseInstruction RiscV.Op + $ RiscV.R register RiscV.DIV register operandRegister2 (RiscV.Funct7 0b0000001) + branchLabel <- createLabel + let branchInstruction = Instruction + $ RiscV.RelocatableInstruction RiscV.Branch + $ RiscV.RBranch branchLabel RiscV.BNE RiscV.Zero operandRegister2 + pure $ mappend statements1 $ Vector.fromList + [ branchInstruction + , Instruction (RiscV.CallInstruction "_divide_by_zero_error") + , JumpLabel branchLabel [] + , divisionInstruction + ] quadruple (LabelQuadruple (Label label)) = pure $ Vector.singleton $ JumpLabel label mempty quadruple (GoToQuadruple label) = pure $ Vector.singleton $ unconditionalJal label quadruple (EqualQuadruple operand1 operand2 goToLabel) |
