Stub the implementation for all phases

1 files changed, 6 insertions, 0 deletions

diff --git a/lib/Language/Elna/Architecture/RiscV.hs b/lib/Language/Elna/Architecture/RiscV.hs
index 5d8c247..f4c3887 100644
--- a/lib/Language/Elna/Architecture/RiscV.hs
+++ b/lib/Language/Elna/Architecture/RiscV.hs
@@ -136,6 +136,7 @@ data Type
     | R XRegister Funct3 XRegister XRegister Funct7
     | U XRegister Word32
     | J XRegister Word32
+    | Type XRegister Funct3 XRegister Funct12 -- Privileged.
 
 data Instruction = Instruction BaseOpcode Type
 
@@ -278,6 +279,11 @@ type' (J rd immediate)
      .|. ((immediate .&. 0x800) `shiftL` 9)
      .|. ((immediate .&. 0x7fe) `shiftL` 20)
      .|. ((immediate .&. 0x100000) `shiftL` 11);
+type' (Type rd funct3' rs1 funct12')
+    = (fromIntegral (xRegister rd) `shiftL` 7)
+    .|. (fromIntegral (funct3 funct3') `shiftL` 12)
+    .|. (fromIntegral (xRegister rs1) `shiftL` 15)
+    .|. (fromIntegral (funct12 funct12') `shiftL` 20);
 
 instruction :: Instruction -> ByteString.Builder.Builder
 instruction (Instruction base instructionType)