Implement division

lib/Language/Elna/RiscV/CodeGenerator.hs

@@ -29,7 +29,15 @@ data Statement
 
 riscVConfiguration :: MachineConfiguration RiscV.XRegister
 riscVConfiguration = MachineConfiguration
-    { temporaryRegister = RiscV.T0
+    { temporaryRegisters =
+        [ RiscV.T0
+        , RiscV.T1
+        , RiscV.T2
+        , RiscV.T3
+        , RiscV.T4
+        , RiscV.T5
+        , RiscV.T6
+        ]
     }
 
 type RiscVStore = Store RiscV.XRegister
@@ -158,6 +166,35 @@ quadruple (ProductQuadruple operand1 operand2 (Store register))
             $ RiscV.BaseInstruction RiscV.Op
             $ RiscV.R register RiscV.MUL register operandRegister
             $ RiscV.Funct7 0b0000001
+quadruple (DivisionQuadruple operand1 operand2 (Store register))
+    | IntOperand immediateOperand1 <- operand1
+    , IntOperand immediateOperand2 <- operand2 =
+        lui (quot immediateOperand1 immediateOperand2) register
+    | VariableOperand variableOperand1 <- operand1
+    , VariableOperand variableOperand2 <- operand2 =
+        let Store operandRegister1 = variableOperand1
+            Store operandRegister2 = variableOperand2
+        in pure $ Instruction
+            $ RiscV.BaseInstruction RiscV.Op
+            $ RiscV.R register RiscV.DIV operandRegister1 operandRegister2 (RiscV.Funct7 0b0000001)
+    | VariableOperand variableOperand1 <- operand1
+    , IntOperand immediateOperand2 <- operand2 =
+        let statements2 = lui immediateOperand2 register
+            Store operandRegister1 = variableOperand1
+        in Vector.snoc statements2
+            $ Instruction
+            $ RiscV.BaseInstruction RiscV.Op
+            $ RiscV.R register RiscV.DIV operandRegister1 register
+            $ RiscV.Funct7 0b0000001
+    | IntOperand immediateOperand1 <- operand1
+    , VariableOperand variableOperand2 <- operand2 =
+        let statements1 = lui immediateOperand1 register
+            Store operandRegister2 = variableOperand2
+        in Vector.snoc statements1
+            $ Instruction
+            $ RiscV.BaseInstruction RiscV.Op
+            $ RiscV.R register RiscV.DIV register operandRegister2
+            $ RiscV.Funct7 0b0000001
 
 loadImmediateOrRegister :: RiscVOperand -> RiscV.XRegister -> (RiscV.XRegister, Vector Statement)
 loadImmediateOrRegister (IntOperand intValue) targetRegister =