Implement division

2024-10-06 18:07:57 +02:00
parent 35742aa525
commit 699cc8684b
13 changed files with 101 additions and 27 deletions
--- a/6
+++ b/6
@ -17,8 +17,9 @@

 # Register allocation

- Temporary variables always use the same register, t0. Allocate registers for
-  temporaries.
+- Each temporary variales gets a tn register where n is the variable index. If
+  there more variables the allocation will fail with out of bounds runtime
+  error. Implement spill over.

 # Prarsing and abstract syntax tree

@ -27,3 +28,4 @@
 # Other

 - Type analysis.
+- Generate call a to _divide_by_zero_error on RiscV.