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Stub the implementation for all phases

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This commit is contained in:
Eugen Wissner
2024-09-08 02:08:13 +02:00
parent a625bbff50
commit 1cbbef19af
13 changed files with 319 additions and 139 deletions
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6
lib/Language/Elna/Architecture/RiscV.hs
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@ -136,6 +136,7 @@ data Type
| R XRegister Funct3 XRegister XRegister Funct7
| U XRegister Word32
| J XRegister Word32
| Type XRegister Funct3 XRegister Funct12 -- Privileged.
data Instruction = Instruction BaseOpcode Type
@ -278,6 +279,11 @@ type' (J rd immediate)
.|. ((immediate .&. 0x800) `shiftL` 9)
.|. ((immediate .&. 0x7fe) `shiftL` 20)
.|. ((immediate .&. 0x100000) `shiftL` 11);
type' (Type rd funct3' rs1 funct12')
= (fromIntegral (xRegister rd) `shiftL` 7)
.|. (fromIntegral (funct3 funct3') `shiftL` 12)
.|. (fromIntegral (xRegister rs1) `shiftL` 15)
.|. (fromIntegral (funct12 funct12') `shiftL` 20);
instruction :: Instruction -> ByteString.Builder.Builder
instruction (Instruction base instructionType)